Chip testing method, device, electronic apparatus and computer readable medium

ABSTRACT

A chip testing method, device, electronic apparatus, and computer readable medium are provided, relating to the field of chip testing. The method includes: determining a language rule of a chip to be tested; determining product and timing specifications of the chip to be tested; selecting a test pattern from a test pattern library according to the language rule and the product and timing specifications; generating a test code according to the product and timing specifications and the test pattern; and automatically testing the chip to be tested by using the test code. The chip testing method, device, electronic apparatus and computer readable medium can automatically generate a big-data test code for complex memories, and rapidly generate, in a standardized way, test codes for DDR4 memories of different specifications, thereby improving the efficiency of chip product verification analysis.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of International PatentApplication No. PCT/CN2019/113246, filed on Oct. 25, 2019, which isbased on and claims priority of the Chinese Patent Application No.201811261790.3, filed on Oct. 26, 2018, and entitled “CHIP TESTINGMETHOD, DEVICE, ELECTRONIC APPARATUS AND COMPUTER READABLE MEDIUM.” Theabove-referenced applications are incorporated herein by reference inits entirety.

TECHNICAL FIELD

The present disclosure relates generally to the technical field of chiptesting and, more specifically, to a chip testing method, apparatus,electronic apparatus, and computer readable medium.

BACKGROUND

With the rapid development in memory technologies and the rapidexpansion of the memory market, memory chips with large capacity, fastread/write speed, and low price are dominating the market. To ensurelong-term reliability of these memory chips, they need to undergometiculous high speed tests before being released to the market.

In the related art regarding the testing of memory products, themajority of work need to be manually done by a tester. The tester firstneeds to confirm a corresponding model and speed for a memory product tobe tested, and then a test scheme suitable for the memory product needsto be selected. After the test scheme is selected, the tester also needsto manually write the test codes. Codes need to be written for each testcommand in a test sequence, and then the memory product can be testedafter the codes have been completed.

The chip testing that relies on manually-written codes requiressubstantial manpower and material resources and thus results in lowefficiency of memory testing. Moreover, with the development in memorytechnologies, more and more high-speed, high-capacity memories come tothe market, and chip testing for these memories requires increasinglycomplicate and voluminous test codes. For high-speed, high-capacitymemories, chip testing with big-data test codes that need to be manuallywritten has become a limiting factor in the development of memorytesting industry.

Therefore, a new chip testing method, device, electronic apparatus, andcomputer readable medium that can address the aforementioned issues aredesired.

The above information is only used to facilitate understanding thebackground of the present disclosure and thus may include informationthat does not constitute prior art known to a person of ordinary skillin the art.

SUMMARY

In view of the limitations of existing technologies described above, thepresent disclosure provides a chip testing method, device, electronicapparatus, and computer readable medium, which can automaticallygenerate a big-data test code for complex memory and improve chiptesting efficiency.

Other features and advantages of the present disclosure will be apparentfrom the following detailed description or obtained in part from thepractice of the disclosure.

One aspect of the present disclosure is directed to a chip testingmethod. The method may include: determining a language rule of a chip tobe tested; determining product and timing specifications of the chip tobe tested; selecting a test pattern from a test pattern libraryaccording to the language rule and the product and timingspecifications; generating a test code according to the product andtiming specifications and the test pattern; and automatically testingthe chip to be tested by using the test code.

In some embodiments of the present disclosure, the method may furtherinclude: generating the test pattern library based on a plurality oftest patterns. The plurality of test patterns may include: a fast readoperation test pattern, a fast write operation test pattern, a fastread/write operation test pattern, a self-refreshing test pattern, arefreshing test pattern, a ZQ calibration test pattern, a mode registersetting test pattern, and a pre-charge power-down test pattern.

In some embodiments of the present disclosure, the chip may comprise amemory chip.

In some embodiments of the present disclosure, the memory chip may be aDDR4 chip.

In some embodiments of the present disclosure, determining the languagerule of the chip to be tested may include: determining a language rulefor the chip to be tested according to a specification document of thechip to be tested.

In some embodiments of the present disclosure, determining the productand timing specifications of the chip to be tested may comprise:determining a memory cell address, a memory row address, a memory columnaddress, and a memory page size of the chip to be tested; anddetermining a model identification, a product identification, andparameters of the chip to be tested.

In some embodiments of the present disclosure, selecting a test patternfrom a test pattern library according to the language rule and theproduct and timing specifications may comprise: determining a databaseof the chip to be tested according to the product and timingspecifications; and selecting the test pattern from the test patternlibrary according to the language rule and the database.

In some embodiments of the present disclosure, selecting a test patternfrom a test pattern library according to the language rule and theproduct and timing specifications may comprise: determining a databaseof the chip to be tested according to the product and timingspecifications; and designating, based on a history product analysis,the test pattern from the test pattern library according to the languagerule and the database.

In some embodiments of the present disclosure, generating a test codeaccording to the product and timing specifications and the test patternmay comprise: inserting a timing sequence into the test patternaccording to the product and timing specifications to generate the testcode.

In some embodiments of the present disclosure, inserting a timingsequence into the test pattern to generate the test code according tothe product and timing specifications may comprise: inserting the timingsequence into the test pattern according to the product and timingspecifications; and converting the inserted timing sequence by ahigh-speed test machine to generate the test code.

Another aspect of the present disclosure is directed to a chip testingdevice. The device may include: a parameter reading interface, a codegenerating module, and a high-speed test machine. The parameter readinginterface may be configured to determine a language rule of a chip to betested, and to determine product and timing specifications of the chipto be tested. The code generating module may be configured to select atest pattern from a test pattern library according to the language ruleand the product and timing specifications, and to generate a test codeaccording to the product and timing specifications and the test pattern.The high-speed test machine may be configured to automatically test thechip to be tested using the test code.

In some embodiments of the present disclosure, the device may furtherinclude: a test pattern library module. The test pattern library modulemay be configured to generate the test pattern library based on aplurality of test patterns. The plurality of test patterns may comprise:a fast read operation test pattern, a fast write operation test pattern,a fast read/write operation test pattern, a self-refreshing testpattern, a refreshing test pattern, a ZQ calibration test pattern, amode register setting test pattern, and pre-charge power-down testpattern.

In some embodiments of the present disclosure, the code generatingmodule may comprise: a selection module, configured to select a testpattern from a test pattern library according to the language rule and adatabase.

Another aspect of the present disclosure is directed to a chip testingdevice. The device may include: an information module, a native randompattern creator, a format conversion module, and a test module. Theinformation module may be configured to acquire related information of achip to be tested. The native random pattern creator may be configuredto generate a target test pattern for testing the chip to be testedaccording to information in the information module and content of adatabase. The format conversion module may be configured to insert atiming sequence into the target test pattern according to product andtiming specifications, and to convert the inserted timing sequence by ahigh-speed test machine to generate a test code. The test module may beconfigured to generate an automated test code.

In some embodiments of the present disclosure, the device may furtherinclude: a pattern library, configured to store a plurality of testpatterns; and a pattern model module, configured to store the targettest pattern. The target test pattern may be one of the plurality oftest patterns.

Another aspect of the present disclosure is directed to an electronicapparatus. The apparatus may include one or more processors and a memorydevice. The memory device may be configured to store one or moreprograms. Upon being executed by the one or more processors, the one ormore programs may cause the one or more processors to perform the chiptest method in any of the aforementioned embodiments.

Another aspect of the present disclosure is directed to a computerreadable medium storing a computer program executable by a processor.Upon being executed by the processor, the computer program may cause theprocessor to perform the chip test method of any of the aforementionedembodiments.

According to the chip testing method, device, electronic apparatus andcomputer readable medium of the present disclosure, a flexiblearchitecture may be constructed specifically for the DDR4 memory test,and the DDR4 memory test code may be automatically generated accordingto the product specification. A big-data test code of for complexmemories may be automatically generated, thereby improving theefficiency of chip product verification analysis.

It should be understood that the above general description and thefollowing detailed description are merely exemplary, and it is notintended to limit the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objectives, features, and advantages of the presentdisclosure will become more apparent after reading the exemplaryembodiments in view of the accompanying drawings. The drawings describedbelow are only some of the embodiments of the present disclosure, andthose skilled in the art can obtain other drawings based on thesedrawings without any creative work.

FIG. 1 shows a flow chart illustrating a chip testing method inaccordance with one embodiment of this invention.

FIG. 2 shows is a schematic diagram of a chip testing method inaccordance with one embodiment of this invention.

FIG. 3 shows a block diagram of a chip testing device in accordance withone embodiment of this invention.

FIG. 4 shows a block diagram of a chip testing device in accordance withanother embodiment of this invention.

FIG. 5 shows a schematic diagram of a chip testing device in accordancewith one embodiment of this invention.

FIG. 6 shows a block diagram of an electronic apparatus in accordancewith one embodiment of this invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments will now be described in detail with reference tothe accompanying drawings. However, the exemplary embodiments can beembodied in a variety of forms and should not be construed to be limitedby the embodiments set forth herein. Instead, providing such embodimentsmay make the present disclosure comprehensive and complete, andcompletely convey the concept of the present disclosure to those skilledin the art. The same reference numerals in the drawings denote the sameor similar parts, and the repeated description thereof will be omitted.

It shall be understood that, although the terms first, second, third,etc. may be used herein to describe various components, these componentsshall not be limited by these terms. These terms are used to distinguishone component from another. Thus, a first component discussed belowcould be termed a second component without departing from the teachingsof the present disclosure. The term “and/or” as used herein includes anyand all combinations of one or more of the associated listed items.

It shall be understood by those skilled in the art that the drawings areonly a schematic diagram of the exemplary embodiments, and the modulesor processes in the drawings are not necessarily required to implementthe disclosure, and therefore are not intended to limit the scope of thedisclosure.

FIG. 1 shows a flow chart showing a chip testing method according to anexemplary embodiment. The chip testing method 10 may include at leaststeps S102 to S110.

As shown in FIG. 1, in step S102, a language rule of a chip to be testedmay be determined. The chip to be tested may include: a memory, whichmay specifically be, for example, DDR4 memory. The language rule of thechip to be tested can be determined according to a specificationdocument of the chip to be tested.

In this application, “DDR” or “DDR SDRAM” may refer to a dual data ratesynchronous dynamic random access memory. DDR4 memory is a newgeneration of memory specifications. Compared with DDR3, a previousgeneration of memory specifications, DDR4 has a 16-bit prefetchmechanism. At the same core frequency, the theoretical speed of DDR4 istwice that of DDR3. DDR4 has more reliable transmission specifications,and thus data reliability is further improved. Moreover, DDR4 has adecreased operating voltage of 1.2V, and thus is more energy efficient.DDR4 is also known as the second generation of memory, developed fromDDR1, DDR2, DDR3 memory.

In one embodiment, the language rule of DDR4 memory can be acquired byreferring to the definition in JEDEC Standard No. 79-4B. JEDEC StandardNo. 79-4B is the instruction manual for DDR4 SDRAM, which includesinformation about the features, functions, AC and DC characteristics,package and ball distribution of DDR4 SDRAM. The purpose of thisstandard is to define the JEDEC minimum standard for x4\x8\x16 DDR4SDRAM from 2 Gbit to 16 Gbit.

In one embodiment, the language rule of a memory may also be acquiredfrom other documents depending on the specifications of the memory.These documents may include, for example: DDR SDRAM STANDARD JESD79;DDR2 SDRAM STANDARD JESD79-2; DDR3 SDRAM STANDARD JESD79-3; andSmartTest 7.4.3 Documentation.

In one embodiment, the language rule of a chip may describe theoperating logic of the chip. The operating logic may include, forexample, when the chip is in an activated state, it can be converted toa memory library activated state by an automatic sequence command, andwhen the chip is in an idle state, it can be converted to an activatedstate by executing a command. The operating logic may include otherlogics relating to the operation of the chip, which is not exhaustivelyenumerated herein.

In step S104, product and timing specifications of the chip to be testedmay be determined.

In one embodiment, determining a product specification of the chip to betested may include determining a memory cell address, a memory rowaddress, a memory column address, and a memory page size of the chip tobe tested.

In one embodiment, determining a timing specification of the chip to betested may include determining a model identifier, a product identifier,and a parameter of the chip to be tested. The chip to be tested mayinclude DDR4 memory, and the product and timing specifications of theDDR4 memory may be defined in JEDEC Standard No. 79-4B.

The speed class of the DDR4 may include, for example,3200/2933/2666/2400/2133/1866 and the like.

Table 1 shows a product specification of the chip according to oneembodiment.

Structure 1 Gb*4 512 Mb*8 256 Mb*16 Memory cell address Number of groups4 4 2 Group address BG0~BG1 BG0~BG1 BG0 Memory cell address in the groupBA0~BA1 BA0~BA1 BA0~BA1 Memory row address  A0~A15  A0~A14  A0~A14Memory column address A0~A9 A0~A9 A0~A9 Memory page size 512 B 1 KB 2 KBStructure 2 Gb*4 1 Gb*8 512 Mb*16 Memory cell address Number of groups 44 2 Group address BG0~BG1 BG0~BG1 BG0 Memory cell address in the groupBA0~BA1 BA0~BA1 BA0~BA1 Memory row address  A0~A16  A0~A15  A0~A15Memory column address A0~A9 A0~A9 A0~A9 Memory page size 512 B 1 KB 2 KBStructure 4 Gb*4 2 Gb*8 1 Gb*16 Memory cell address Number of groups 4 42 Group address BG0~BG1 BG0~BG1 BG0 Memory cell address in the groupBA0~BA1 BA0~BA1 BA0~BA1 Memory row address  A0~A17  A0~A16  A0~A16Memory column address A0~A9 A0~A9 A0~A9 Memory page size 512 B 1 KB 2 KB

Table 2 shows a timing specification of the chip according to oneembodiment:

Model identifier DDR4-2400P DDR4-2400R Product identifier 15-15-1516-16-16 Product parameters Symbol min max min max Internal read commandtAA 12.50 18.00 13.32 18 to the first data Internal read command tAA_DBItAA(min) tAA(max) tAA(min) tAA(max) to read the first data of +3nCK+3nCK +3nCK +3nCK data inversion (DBI) Open (ACT) to internal tRCD 12.5013.32 read or write delay time Close (PRE) command tRP 12.50 13.32 cycleOpen (ACT) to close tRAS 32   9*tREFI 32   9*tREFI (PRE) command periodOpen (ACT) to open tRC 44.50 45.32 (ACT) or close (PRE) command

In step S106, a test pattern may be selected from a test pattern libraryaccording to the language rule and the product and timingspecifications. For example, step S106 may include: determining adatabase of the chip to be tested according to the product and timingspecifications, and selecting the test pattern from the test patternlibrary according to the language rule and the database.

In one embodiment, the method may further include generating the testpattern library based on a plurality of test patterns. The plurality oftest patterns may comprise: an X-direction/Y-direction fast writeoperation test pattern (X/Y fast Write pattern), an X direction/Ydirection fast read operation test pattern (X/Y fast Read pattern), an Xdirection/Y direction fast read/write operation test pattern (X/Y fastWrite/Read pattern), a self-refreshing test pattern (Self-refresh), arefreshing test pattern (Refreshing), a ZQ calibration test pattern (ZQcalibration), a pre-charge power-down test pattern (Pre-chargePower-down), and a mode register setting test pattern (Mode RegisterSet).

In one embodiment, selecting a test pattern from a test pattern libraryaccording to the language rule and the database may comprise: firstselecting a plurality of test patterns that meet the condition in thetest pattern library according to the language rule. Then the pluralityof test patterns may be subjected to a secondary screening according tothe content in the database corresponding to the chip to be tested, sothat the patterns that do not meet the requirements of the chip may beremoved. Finally, a test pattern may be selected from the rest of theplurality of test patterns.

In one embodiment, the number of selected test pattern may be one ormore, which is not limited in this disclosure.

In one embodiment, the method may include: determining a database of thechip to be tested according to the product and timing specifications;and designating the test pattern from the test pattern library accordingto the language rule and the database. Specifically, the method maycomprise: first selecting a plurality of test patterns that meet thecondition in the test pattern library according to the language rule.Then the plurality of test patterns may be subjected to a secondaryscreening according to the content in the database corresponding to thechip to be tested, so that the patterns that do not meet therequirements of the chip may be removed. Finally, according to theexpert's opinions or based on the experience from history productanalysis, a target test pattern may be designated from the rest of theplurality of test patterns.

In step S108, a test code may be generated according to the product andtiming specifications and the test pattern. In one example, step S108may include: inserting a timing sequence into the test pattern accordingto the product and timing specifications to generate the test code.

In one embodiment, inserting a timing sequence into the test patternaccording to the product and timing specifications to generate the testcode may include: inserting the timing sequence into the test patternaccording to the product and timing specifications; and converting theinserted timing sequence by a high-speed test machine to generate thetest code.

In one embodiment, the high-speed test machine may be an HSM6800high-speed test machine, and the HSM6800 high-speed test machine mayhave a programmable function to support the tests for advanced featuresof GDDR5 (Graphics Double Data Rate, version 5), which includes AddressBus Inversion (ABI), Data Bus Inversion (DBI), and Cyclic RedundancyCheck (CRC). In addition, the test machine can test the memory of acommon 8-bit data frame (frame) due to its flexible architecture, andcan also be extended to test 10-bit data frame memory in the future.Thus the test machine can meet the requirements in performance,functionality and cost for the testing of all kinds of high-speedmemories.

In step S110, the chip to be tested may be automatically tested usingthe test code. An automated test code may be generated by using theprogrammable function of the HSM6800 high-speed test machine and thelanguage rules of DDR4 memory, which enables the test machine toautomatically generate a big-data test code for memories. The generatedtest code may be used to simulate the system environment test toexpedite the die test of the DDR4 memory.

In one embodiment, during the test, each write action may be recorded bythe database while the read actions may be generated based on thecurrent contents of the database.

FIG. 2 shows a schematic diagram of a chip testing method in accordancewith one embodiment of this invention. FIG. 2 exemplarily shows apattern of test codes for DDR4 memories of different specificationsrapidly generated by the chip testing method of the present disclosure.

As shown in FIG. 2, the language rule and the product and timingspecifications of the chip to be tested may be determined first. Thenthe test pattern may be selected from the test pattern library accordingto the language rule and the product and timing specifications. Then thetest code may be automatically generated according to the product andtiming specifications and the test pattern, and the specific pattern ofthe test code may be a pulse code composed of 0 or 1.

According to the schematic diagram of the chip testing method as shownin FIG. 2, a user may inspect the relevant test parameters of the testpattern from the parameter setting area 202, and, if necessary, modifythe test parameters. The user can inspect various test commandscorresponding to the test pattern from the command selection area 204 tofurther understand the test. A specific test code is shown in the coderegion 206, and the specific test code consists of a pulse sequencecomposed of 0 or 1, wherein 1 may represent a high voltage level, and 0may represent a low voltage level.

According to the chip testing method of the present disclosure, the testpattern may be selected from the test pattern library according to thelanguage rule and the product and timing specifications. The test codemay be generated according to the product and timing specifications andthe test pattern. Therefore, a big-data test code of complex memory canbe generated automatically, and the test codes for DDR4 memories ofdifferent specifications can be generated rapidly in a standardized way,thereby improving the efficiency of chip product verification analysis.

According to the chip testing method of the present disclosure, aflexible architecture may be constructed specifically for the DDR4memory test, and the DDR4 memory test code may be automaticallygenerated according to the content of the product specification.Compared to manually written codes, the automatically-generated codesmay be created with much higher efficiency. Thus, the problem associatedwith manually writing a big-data test code for complex DDR4 memory inthe related art can be solved.

According to the chip testing method of the present disclosure, the testcodes for DDR4 memories of different specifications can be rapidlygenerated in a standardized way. Thus human errors that are inevitablein manual coding can be avoided, and the quality of the test codes maybe improved.

According to the chip testing method of the present disclosure, detailedcoding procedural information can be provided, and each procedure in thetest coding can be presented to a human inspector. Therefore, in case anerror is reported during a test, the human inspector can perform apositioning analysis according to the test code to quickly identify andremedy any issue, thereby improving the efficiency of the productanalysis.

This invention further presents a chip testing device based on theaforementioned chip testing method. The device may be configured toimplement the chip testing method according to the embodiments of thepresent disclosure. Any detail not disclosed herein can be obtained byreferring to the embodiments for the method of the present disclosure.

FIG. 3 shows a block diagram of a chip testing device in accordance withone embodiment of this invention. The chip testing device 30 may includea parameter reading interface 302, a code generating module 304, and ahigh-speed test machine 306.

The parameter reading interface 302 may be configured to determine alanguage rule of the chip to be tested, and to determine product andtiming specifications of the chip to be tested. The chip to be testedmay include: a memory, which may be, for example, DDR4 memory.

In one embodiment, the product and timing specifications of the DDR4memory and the language specifications of the DDR4 memory may beacquired by referring to the definitions in JEDEC Standard No. 79-4B.

The code generating module 304 may be configured to select a testpattern from a test pattern library according to the language rule andthe product and timing specifications, and to generate a test codeaccording to the product and timing specifications and the test pattern.

In one embodiment, the code generating module 304 may determine adatabase of the chip to be tested according to the product and timingspecifications, and select the test pattern from the test patternlibrary according to the language rule and the database.

In one embodiment, the code generating module 304 may insert a timingsequence into the test pattern according to the product and timingspecifications; and convert the inserted timing sequence by a high-speedtest machine to generate the test code.

The high-speed test machine 306 may be configured to automatically testthe chip to be tested using the test code. An automated test code may begenerated by the programmable function of the high-speed test machine306 and the language rule of the DDR4 memory, which enables the testmachine to automatically generate a big-data test code for memory. Thegenerated test code may be used to simulate the system environment testto expedite the die test of the DDR4 memory.

FIG. 4 shows a block diagram of a chip testing device in accordance withanother embodiment of this invention. As shown in FIG. 4, the chiptesting device 40 may further include a test pattern library module 402in addition to the chip testing device 30 of FIG. 3.

The test pattern library module 402 may be configured to generate thetest pattern library based on a plurality of test patterns.

In one embodiment, the test pattern library may be generated based on aplurality of test patterns. The plurality of test patterns may include:an X-direction/Y-direction fast write operation test pattern, anX-direction/Y-direction fast read operation test pattern, anX-direction/Y-direction fast read/write operation test pattern, aself-refreshing test pattern, a refreshing test pattern, a ZQcalibration test pattern, a pre-charge power-down test pattern, and amode register setting test pattern.

According to the chip testing device of the present disclosure, the testpattern may be selected from the test pattern library according to thelanguage rule and the product and timing specifications; and the testcode may be generated according to the product and timing specificationsand the test pattern. Therefore, a big-data test code of complex memorycan be generated automatically, thereby improving the efficiency of chipproduct verification analysis.

FIG. 5 shows a schematic diagram of a chip testing device in accordancewith one embodiment of this invention. As shown in FIG. 5, the chiptesting device 50 may include: an information module 502, a patternlibrary 504, a native random pattern creator 506, a database 508, apattern model module 510, a format conversion module 512, and a testmodule 514.

The information module 502 may be configured to acquire relatedinformation of a chip to be tested, and the information module 502 maybe configured to determine a language rule of the chip to be tested. Theinformation module 502 may also be configured to determine the productand timing specifications of the chip to be tested.

The pattern library 504 may be configured to store a plurality of testpatterns. The plurality of test patterns may include, for example, anX-direction/Y-direction fast write operation test pattern, anX-direction/Y-direction fast read operation test pattern, anX-direction/Y-direction fast read/write operation test pattern, aself-refreshing test pattern, a refreshing test pattern, a ZQcalibration test pattern, a pre-charge power-down test pattern, and amode register setting test pattern.

The native random pattern creator 506 may be configured to generate atest pattern from the pattern library 504 based on the information inthe information module 502 and content in the database 508. Based ondifferent combinations of a test pattern from the pattern library 504and information of the chip to be tested (e.g., the language rule, theproduct and timing specification of the chip to be tested) in theinformation module 502, and the content in the database 508, the nativerandom pattern creator 506 may generate a large number of test patternsfor testing the chip to be tested.

In some embodiments, the content in the database 508 may include datathat may be used to generate the test patterns for testing.Additionally, after a test on a chip is completed, the content in thedatabase 508 may be used to compare with results returned from the testto determine an outcome of the test.

The pattern model module 510 may be configured to store the generatedtest patterns.

The format conversion module 512 may be configured to insert a timingsequence into the generated test patterns using product and timingspecifications, and to convert the inserted timing sequence by ahigh-speed test machine to generate a test code.

The test module 514 may be configured to generate an automated test codeusing the programmable function of a high-speed test machine and thelanguage rules of DDR4 memory, which may enable the test machine toautomatically generate a big-data test code for memories. The generatedtest code may be used to simulate the system environment test toexpedite the die test of the DDR4 memory.

In some embodiments, the test module 514 may be a high-speed testmachine, such as an HSM6800 high-speed test machine.

FIG. 6 shows a block diagram of an electronic apparatus in accordancewith one embodiment of this invention.

An electronic apparatus 200 according to an embodiment of the presentdisclosure is described below with reference to FIG. 6. The electronicapparatus 200 shown in FIG. 6 is merely an example and should not limitthe scope of function and use of apparatus according to the embodimentsof the present disclosure.

As shown in FIG. 6, the electronic apparatus 200 may be implemented as ageneral-purpose computing device. The components of the electronicapparatus 200 may include, but are not limited to, at least oneprocessing unit 210, at least one storage unit 220, a bus 230 connectingdifferent system components (including the storage unit 220 and theprocessing unit 210), a display unit 240, and the like.

The storage unit 220 may store a program code, and the program code canbe executed by the processing unit 210, such that the processing unit210 performs the method in any of the aforementioned embodiments. Forexample, the processing unit 210 can perform the method as shown in FIG.1.

The storage unit 220 may include a readable medium in the form ofvolatile memory, such as a random access memory (RAM) 2201 and/or acache memory 2202, and may further include a read-only cache memory(ROM) 2203.

The storage unit 220 may also include a program/utility 2204 having aset (at least one) of the program modules 2205 including but not limitedto: an operating system, one or more applications, other programmodules, and program data, each of or some combinations of theseexamples may include an implementation of a network environment.

Bus 230 may represent one or more of several types of bus structures,which may include a storage unit bus or a storage unit controller, aperipheral bus, a graphics acceleration port, a processing unit, or alocal bus using any of the bus structures.

The electronic apparatus 200 can also communicate with one or moreexternal devices 300 (e.g., a keyboard, pointing device, Bluetoothdevice, etc.), and can also communicate with one or more devices thatenable the user to interact with the electronic apparatus 200, and/orwith any device (e.g., a router, modem, etc.) that enables theelectronic apparatus 200 to communicate with one or more other computingdevices. The communication can take place via an input/output (I/O)interface 250. Moreover, electronic apparatus 200 can also communicatewith one or more networks (e.g., a local area network (LAN), a wide areanetwork (WAN), and/or a public network, such as the Internet) via anetwork adapter 260. The network adapter 260 can communicate with othermodules of electronic apparatus 200 via Bus 230. It should be understoodthat although not shown in the figures, other hardware and/or softwaremodules may be utilized in conjunction with electronic apparatus 200,including but not limited to: microcode, device drivers, redundantprocessing units, external disk drive arrays, RAID systems, tape drives,and data backup storage systems, etc.

Based on the description of the above embodiments, those skilled in theart will readily understand that the exemplary embodiments describedherein may be implemented by software, hardware, or the combination ofsoftware and necessary hardware. Therefore, the technical solutionaccording to an embodiment of the present disclosure may be embodied inthe form of a software product, which may be stored in a non-volatilestorage medium (which may be a CD-ROM, a USB flash drive, a mobile harddisk, etc.) or on a network. A plurality of commands is included tocause a computing device (which may be a personal computer, server, ornetwork device, etc.) to perform the above method in accordance with anembodiment of the present disclosure, which may include: determining alanguage rule of a chip to be tested; determining product and timingspecifications of the chip to be tested; selecting a test pattern from atest pattern library according to the language rule and the product andtiming specifications; generating a test code according to the productand timing specifications and the test pattern; and automaticallytesting the chip to be tested by using the test code.

It will be understood by those skilled in the art that the above variousmodules may be distributed in the device according to the description ofthe embodiments, or may be correspondingly changed in one or moredevices different from the embodiment. The modules of the aboveembodiments may be combined into one module or may be further dividedinto a plurality of sub-modules.

Based on the description of the above embodiments, those skilled in theart can easily understand that the exemplary embodiments describedherein may be implemented by software, or may be implemented by softwarein combination with necessary hardware. Therefore, the technicalsolution according to an embodiment of the present disclosure may beembodied in the form of a software product, which may be stored in anon-volatile storage medium (which may be a CD-ROM, a USB flash drive, amobile hard disk, etc.) or on a network. A plurality of commands areincluded to cause a computing device (which may be a personal computer,server, mobile terminal, or network device, etc.) to perform a method inaccordance with an embodiment of the present disclosure.

The exemplary embodiments of the present disclosure have beenparticularly shown and described above. It should be understood that theinvention is not limited to the details of the embodiments of thedisclosure.

The invention claimed is:
 1. A chip testing method, comprising:determining a language rule of a chip to be tested; determining productand timing specifications of the chip to be tested; generating, based ona plurality of test patterns, a test pattern library, wherein theplurality of test patterns comprises: a fast read operation testpattern, a fast write operation test pattern, a fast read/writeoperation test pattern, a self-refreshing test pattern, a refreshingtest pattern, a ZQ calibration test pattern, a mode register settingtest pattern, and a pre-charge power-down test pattern; selecting,according to the language rule and the product and timingspecifications, a test pattern from the test pattern library;generating, according to the product and timing specifications and theselected test pattern, a test code; and automatically testing, using thetest code, the chip to be tested.
 2. The chip testing method of claim 1,wherein the chip comprises a memory chip.
 3. The chip testing method ofclaim 2, wherein the memory chip is a DDR4 chip.
 4. The chip testingmethod of claim 2, wherein determining a language rule of the chip to betested comprises: determining, according to a specification document ofthe chip to be tested, a language rule for the chip to be tested.
 5. Thechip testing method of claim 2, wherein determining product and timingspecifications of the chip to be tested comprises: determining a memorycell address, a memory row address, a memory column address, and amemory page size of the chip to be tested; and determining a modelidentification, a product identification, and parameters of the chip tobe tested.
 6. The chip testing method of claim 1, wherein selecting,according to the language rule and the product and timingspecifications, a test pattern from the test pattern library comprises:determining, according to the product and timing specifications, adatabase of the chip to be tested; and selecting, according to thelanguage rule and the database, the test pattern from the test patternlibrary.
 7. The chip testing method of claim 1, wherein selecting,according to the language rule and the product and timingspecifications, a test pattern from the test pattern library comprises:determining, according to the product and timing specifications, adatabase of the chip to be tested; and designating, based on a historyproduct analysis and according to the language rule and the database,the selected test pattern from the test pattern library.
 8. The chiptesting method of claim 1, wherein generating, according to the productand timing specifications and the test pattern, a test code comprises:inserting, according to the product and timing specifications, a timingsequence into the selected test pattern to generate the test code. 9.The chip testing method of claim 8, wherein inserting, according to theproduct and timing specifications, a timing sequence into the selectedtest pattern to generate the test code comprises: inserting, accordingto the product and timing specifications, the timing sequence into theselected test pattern; and converting, by a high-speed test machine, theselected test pattern with the timing sequence to generate the testcode.
 10. A chip testing device, comprising: a parameter readinginterface, configured to determine a language rule of a chip to betested, and to determine product and timing specifications of the chipto be tested; a test pattern library module, configured to generate,based on a plurality of test patterns, a test pattern library, whereinthe plurality of test patterns comprises: a fast read operation testpattern, a fast write operation test pattern, a fast read/writeoperation test pattern, a self-refreshing test pattern, a refreshingtest pattern, a ZQ calibration test pattern, a mode register settingtest pattern, and pre-charge power-down test pattern; a code generatingmodule, configured to select, according to the language rule and theproduct and timing specifications, a test pattern from the test patternlibrary, and to generate, according to the product and timingspecifications and the selected test pattern, a test code; and ahigh-speed test machine, configured to automatically test, using thetest code, the chip to be tested.
 11. The chip testing device of claim10, wherein the code generating module comprises: a selection module,configured to select, according to the language rule and a database, thetest pattern from the test pattern library.
 12. A chip testing device,comprising: an information module, configured to acquire relatedinformation of a chip to be tested; a pattern library, configured tostore a plurality of test patterns, wherein the plurality of testpatterns comprises: a fast read operation test pattern, a fast writeoperation test pattern, a fast read/write operation test pattern, aself-refreshing test pattern, a refreshing test pattern, a ZQcalibration test pattern, a mode register setting test pattern, and apre-charge power-down test pattern; a native random pattern creatorconfigured to generate a target test pattern for testing the chip to betested according to information in the information module and content ofa database, wherein the target test pattern is one of the plurality oftest patterns; a format conversion module, configured to insert,according to product and timing specifications, a timing sequence intothe target test pattern, wherein the target test pattern with the timingsequence is converted, by a high-speed test machine, to generate a testcode, wherein the test code is configured to automatically test the chipto be tested using the target test pattern with the timing sequence. 13.The chip testing device of claim 12, further comprising: a pattern modelmodule, configured to store the target test pattern.
 14. An electronicapparatus, comprising: one or more processors; and a memory device,configured to store one or more programs; wherein, upon being executedby the one or more processors, the one or more programs cause the one ormore processors to perform operations, comprising: determining alanguage rule of a chip to be tested; determining product and timingspecifications of the chip to be tested; generating, based on aplurality of test patterns, a test pattern library, wherein theplurality of test patterns comprises: a fast read operation testpattern, a fast write operation test pattern, a fast read/writeoperation test pattern, a self-refreshing test pattern, a refreshingtest pattern, a ZQ calibration test pattern, a mode register settingtest pattern, and a pre-charge power-down test pattern; selecting,according to the language rule and the product and timingspecifications, a test pattern from the test pattern library;generating, according to the product and timing specifications and theselected test pattern, a test code; and automatically testing, using thetest code, the chip to be tested.
 15. A non-transitory computer readablemedium, storing a computer program executable by a processor, wherein,upon being executed by the processor, the computer program causes theprocessor to perform operations, comprising: determining a language ruleof a chip to be tested; determining product and timing specifications ofthe chip to be tested; generating, based on a plurality of testpatterns, a test pattern library, wherein the plurality of test patternscomprises: a fast read operation test pattern, a fast write operationtest pattern, a fast read/write operation test pattern, aself-refreshing test pattern, a refreshing test pattern, a ZQcalibration test pattern, a mode register setting test pattern, and apre-charge power-down test pattern; selecting, according to the languagerule and the product and timing specifications, a test pattern from thetest pattern library; generating, according to the product and timingspecifications and the selected test pattern, a test code; andautomatically testing, using the test code, the chip to be tested.